A solid state device (SSD) includes a plurality of NAND devices organized into banks which process commands and operations. SSDs include a scheduler which determines an order in which commands, including read, write, and erase commands, should be sent to the banks such that overall progress is made on the commands in the queues. This includes ensuring that low-latency operations such as reads are not queued behind longer-latency operations such as erases, and ensuring that the order of requests from application block requests, meta-data requests, and garbage collection requests are appropriately handled. In some cases, the scheduler manages a power consumption of the device as a whole. Since each of reads, writes, and erases consume different power, the operation scheduler may control overall device power consumption by controlling how many of each operation is active at a time.
Traditionally, command scheduling systems are implemented with an individual scheduler assigned to each bank of devices. The scheduler determines the optimal arrangement of priority and normal priority commands to be transmitted to the bank of devices. The schedule of commands transmitted to the bank of devices allows the system to more efficiently transmit and execute commands.
Multiple banks of NAND devices can be driven in parallel to increase the command transfer efficiency. One parallel operating method is a technique for interleaving a series of commands to a plurality of banks of NAND devices connected to the same channel (known as “bank interleaving”). The process of bank interleaving increases the efficiency of the execution of commands on the SSD by optimizing the usage of the channel and allows the banks to process commands in parallel.
Bank interleaving maximizes the commands sent to the banks in a given amount of time. For a command is that includes a latency time (for example, a write command), the time that the system waits for the response from the bank would be unused without bank interleaving. This contributes to an inefficiency of the system.
In systems which make use of bank interleaving, a scheduler sends a first command including a sequence of instructions to a bank over a channel. The scheduler then determines an efficient use of the latency time associated with the sequence of instructions and sends additional commands to other banks over a common channel. An operation scheduler schedules read, write, and erase operations within banks of devices over a memory channel or memory channel bus. The operation scheduler may receive various inputs including the operations currently being executed and operations in the command or operations queue.
Bank interleaving is typically implemented using a software based logic system in which a command scheduler repeatedly iterates through a series of loops in order to determine an optimal schedule of commands. However, using software logic to determine a schedule of interleaved commands quickly becomes bulky and time delays are introduced when scaled up due to the number of inputs required to efficiently schedule the commands. For example, the determination of an optimal schedule of commands relies on knowledge of a large number of variables including information related to the status of each bank of devices, the command currently being executed by each bank, the time that each of the command will take to be completed, and a status of each of the queues of commands waiting to be transmitted to the banks. While a software-based loop of code can iterate through this information for a small number of banks to determine a next command to be transmitted, as the number of banks sharing a channel is increased the code becomes unwieldy and the processing time for each determination suffers. Accordingly, there is a long-felt need to correct the problems inherent to present day systems.